A variety of highly advanced electronic devices using heterojunctions are developed as electronic devices using GaAs-based or other compound semiconductor crystals. The performance of these electronic devices depends on the crystallinity of the compound semiconductor crystals. Therefore, high-quality crystal thin films are required. When electronic devices using GaAs-based compound semiconductor crystals are manufactured, a thin film is grown on a base wafer made of GaAs, or Ge whose lattice constant is very close to the lattice constant of GaAs, or the like due to requirements including the fact that a lattice match is necessary at the hetero interface.
Patent Document 1 discloses a semiconductor device that has a limited epitaxial region that is grown on a wafer having a lattice mismatch or a wafer having a high dislocation defect density. Non-Patent Document 1 discloses a low-dislocation-density GaAs epitaxial layer grown on a Ge-coated Si wafer by means of lateral epitaxial overgrowth. Non-Patent Document 2 discloses a technique to form, on a Si wafer, a Ge epitaxial growth layer (hereinafter, may be referred to as a Ge epilayer) with high-quality. According to this technique, the Ge epilayer is first formed on a limited region of the Si wafer and then subjected to thermal cycle annealing. This enables the Ge epilayer to achieve an average dislocation density of 2.3×106 cm−2.    Patent Document 1: JP 04-233720 A    Non-Patent Document 1: B. Y. Tsaur et al., “Low-dislocation-density GaAs epilayers grown on Ge-coated Si substrates by means of lateral epitaxial overgrowth,” Appl. Phys. Lett. 41(4)347-349, 15 Aug. 1982    Non-Patent Document 2: Hsin-Chiao Luan et al., “High-quality Ge epilayers on Si with low threading-dislocation densities,” APPLIED PHYSICS LETTERS, VOLUME 75, NUMBER 19, 8 Nov. 1999